Bowed wafers enter the system at two cassette tilt stations. Wafer handling is via a robot fitted with an edge grip end effector. Wafers are oriented on a notch finder, with wafer ID captured by a ...

The company also announced an even more ambitious technology named System-on-Wafer (SoW) that will allow for 3D stacking of logic and memory directly on top of a 300mm wafer-sized chip.